兜兜转转又回来学硬件了,哎,命啊!
我的答案(有bug):
module top_module ( input a, input b, output out ); wire w1; wire w2; wire w3; mod_a mod_a_inst1( .in1(w1), .in2(w2), .out(w3) ); assign w1 = a; assign w2 = b; assign w3 = out; //错误在这看出来了吗?! endmodule