序言
MIPI D-PHY TX端的一致性测试内容如下,总共分为6组,因产品应用场景的需求限制,小编在日常工作中,更多地关注红色所标识的测试内容,接下来,小编将分为三个章节,具体解析下Group3~5的测试内容;
Group 1 (1.1.x) verifies various requirements specific to Data Lane LP-TX signaling
Group 2 (1.2.x) verifies various requirements specific to Clock Lane LP-TX signaling
Group 3 (1.3.x) verifies various requirements specific to Data Lane HS-TX signaling
Group 4 (1.4.x) verifies various requirements specific to Clock Lane HS-TX signaling
Group 5 (1.5.x) verifies various requirements specific to HS-TX Clock-to-Data-Lane timing
Group 6 (1.6.x) verifies various requirements specific to Initialization, ULPS, and BTA behavior
本文讲解的是Group 3测试组的第一部分(内容较多,小编只能边写边发布),实测用例基于Keysight MSOS804A示波器的MIPI模板测试方案。
正文
Test 1.3.1 – Data Lane HS Entry: Data Lane TLPX Value
测试目的:验证
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