library ieee;--库文件引用
use ieee.std_logic_1164.all;
entity addr is
port(a,b,cin : in std_logic;--端口配置
sum,cout : out std_logic);
end entity addr;
architecture rtl of addr is--结构体配置
begin
sum <=a xor b xor cin;
cout <=(a and b) or (a and cin) or (b and cin);
end architecture rtl;