1. introduction
PHY Interface for the PCI Express and USB 3.0 Architectures
USB SuperSpeed PHY Layer
The USB SuperSpeed PHY Layer handles the low level USB SuperSpeed protocol and signaling.
This includes features such as; data serialization and de-serialization, 8b/10b encoding, analog
buffers, elastic buffers and receiver detection. The primary focus of this block is to shift the clock
domain of the data from the USB SuperSpeed rate to one that is compatible with the general logic
in the ASIC.
Some key features of the USB SuperSpeed PHY are:
• Standard PHY interface enables multiple IP sources for USB SuperSpeed Link Layer and provides a target interface for USB SuperSpeed PHY vendors.
• Supports 5.0 GT/s serial data transmission rate
• Utilizes 8-bit, 16-bit
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