In this blog, I’m going to give some instructions about yosys & yosys-abc in Linux.
Environment
yosys 0.7 (gcc 5.4.0, ubuntu 16.04) (But I’m using ubuntu 18.04)
yosys-abc 1.01
Brief introduction
Yosys stands for Yosys Open SYnthesis Suite (what a recursive acronym!). It is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Here, we are going to use it to convert Verilog into BLIF.
Official website: http://www.clifford.at/yosys/
Github: https://github.com/YosysHQ/yosys
Yosys-abc is a growing software system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. It is developed by Berkeley Verification and Synthesis Research Center.
Here, we are going to use it to convert BLIF into BENCH.
Official website: https://people.eecs.berkeley.edu/~alanmi/abc/
Codes
