1.创建具有高电平有效同步复位的8 D触发器。触发器必须重置为0x34而不是零。所有DFF应由clk的负边缘触发。
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always@(negedge clk)begin
if (reset)
q <= 8'h34; //0x指十六进制
else
q <= d;
end
endmodule
2.创建具有高电平有效异步复位的8 D触发器。
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always@(posedge clk or posedge areset)begin
if(areset)
q <= 8'd0;
else
q <= d;
end
endmodule
3.创建16个D触发器。有时只修改一组触发器的一部分很有用。字节使能输入控制在该周期是否应写入16个寄存器的每个字节。byteena [1]控制高字节d [15:8],而byteena [0]控制低字节d [7:0]。
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always@(posedge clk)begin
if(~resetn)
q <= 16'd0;
else if (byteena[0] == 1'b1 | byteena[1] == 1'b1)begin
if(byteena[0] == 1'b1)
q[7:0] <= d[7:0];
if(byteena[1] == 1'b1)
q[15:8] <= d[15:8];
end
end
endmodule
4.如下
module top_module (
input d,
input ena,
output q);
assign q = ena ? d : q; //锁存器在ena为1时,输出d,为0时保持
endmodule
5.如下
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q);
always@(posedge clk or posedge ar)begin
if(ar)
q <= 1'b0;
else
q <= d;
end
endmodule
6.如下
module top_module (
input clk,
input d,
input r, // synchronous reset
output q);
always@(posedge clk)begin
if(r)
q <= 1'b0;
else
q <= d;
end
endmodule
7.如下
module top_module (
input clk,
input in,
output out);
always@(posedge clk)begin
out = out ^ in;
end
endmodule
8.如下
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
reg temp;
assign temp = L ? r_in : q_in;
always@(posedge clk)begin
Q <= temp;
end
endmodule
9.如下
module top_module (
input clk,
input w, R, E, L,
output Q
);
reg temp;
assign temp = L ? R : (E ? w : Q);
always@(posedge clk)begin
Q <= temp;
end
endmodule
10.如下
module top_module (
input clk,
input x,
output z
);
reg q1,q2,q3;
always@(posedge clk)begin
q1 = q1 ^ x;
q2 = ~q2 & x;
q3 = ~q3 | x;
end
assign z = ~(q1 | q2 | q3);
endmodule
11.如下
module top_module (
input clk,
input j,
input k,
output Q);
always@(posedge clk)begin
Q <= j & ~Q | ~k & Q;
end
endmodule
12.如下
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] temp;
always @(posedge clk) begin
temp <= in;
pedge <= ~temp & in;
end
endmodule
13.如下
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] in1;
always@(posedge clk)begin
in1 <= in;
anyedge = in & ~in1 | ~in & in1;
end
endmodule
14.如下
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] temp;
reg [31:0] capt;
//一级缓存
always@(posedge clk)begin
temp <= in;
end
//组合逻辑的捕获信号
assign capt = ~in & temp;
//保持每个always块只有一个输出
always@(posedge clk)begin
if(reset)
out <= 32'd0;
else begin
for(integer i = 0;i < 32;i++)begin
if(capt[i])
out[i] <= 1'b1;
end
end
end
endmodule
15.如下
module top_module (
input clk,
input d,
output q
);
reg q1,q2;
assign q = clk ? q1 :q2;// 当前clk为1,则上一时钟为上升沿,为0,则反之
//从上升沿和下降沿进行采样
always@(posedge clk)begin
q1 <= d;
end
always@( negedge clk)begin
q2 <= d;
end
endmodule