今天来分享一下关于FPGA设计的文章,如何用半加器和全加器构成四位全加器~
首先,我们看一位半加器的代码:
1.一位半加器的程序代码及RTL图
library ieee;
use ieee.std_logic_1164.all;
entity halfadd is
port(a,b:in std_logic;
s,c:out std_logic);
end;
architecture rtl of halfadd is
begin
s<=a xor b;
c<=a and b;
end;
再看一位全加器的程序代码:
2.一位全加器的程序代码及RTL图
library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
port(a,b,cin:in std_logic;
ss,cc:out std_logic);
end;
architecture rtl of fulladd is
component halfadd is
port(a,b:in std_logic;
s,c:out std_logic);
end component;
signal s1,c1,c2:std_logic;
begin
u1:halfadd port map(a,b,s1,c1);
u2:halfadd port map(s1,cin,ss,c2);
cc<=c1 or c2;
end;
最后结合上面,我们来看四位全加器的程序:
3.四位全加器的程序
library ieee;
use ieee.std_logic_1164.all;
entity full4add is
port(a,b:in std_logic_vector(3 downto 0);
sum:out std_logic_vector(3 downto 0);
carry:out std_logic);
end;
architecture rtl of full4add is
component halfadd is
port(a,b:in std_logic;
s,c:out std_logic);
end component;
component fulladd is
port(a,b,cin:in std_logic;
ss,cc:out std_logic);
end component;
signal cc0,cc1,cc2:std_logic;
begin
u1:halfadd port map(a(0),b(0),sum(0),cc0);
u2:fulladd port map(cc0,a(1),b(1),sum(1),cc1);
u3:fulladd port map(cc1,a(2),b(2),sum(2),cc2);
u4:fulladd port map(cc2,a(3),b(3),sum(3),carry);
end;
这里最后我们只用全加器来看看如何实现四位全加器:
4.只用全加器实现四位全加器
library ieee;
use ieee.std_logic_1164.all;
entity full4add is
port(a,b:in std_logic_vector(3 downto 0);
sum:out std_logic_vector(3 downto 0);
carry:out std_logic);
end;
architecture rtl of full4add is
component halfadd is
port(a,b:in std_logic;
s,c:out std_logic);
end component;
component fulladd is
port(a,b,cin:in std_logic;
ss,cc:out std_logic);
end component;
signal cc0,cc1,cc2:std_logic;
begin
u1:fulladd port map('0',a(0),b(0),sum(0),cc0);
u2:fulladd port map(cc0,a(1),b(1),sum(1),cc1);
u3:fulladd port map(cc1,a(2),b(2),sum(2),cc2);
u4:fulladd port map(cc2,a(3),b(3),sum(3),carry);
end;
好了,分享就到这里了~
本人水平有限,上述信息仅供学习参考,如有错误和不妥之处,请多多指教。
另外创作不易,请勿抄袭,如果有帮助到大家的话希望大家可以点个赞,谢谢~