HDLBits — Verilog Practice(每日一题)
一、Getting Started
1、Getting Started
问题描述
Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).
构建一个没有输入和一个输出的电路。该输出应始终驱动 1(或逻辑高电平)。
代码
module top_module( output one );
// Insert your code here
assign one = 1'b1;
endmodule