VHDL - PhysDesignRules：367

当我尝试从 VHDL 代码合成、实现和生成程序文件时，我收到警告。

当我尝试合成时出现此错误

WARNING:Xst:647 - Input <BTN_3> is never used. 
    This port will be preserved and left unconnected if it 
    belongs to a top-level block or it belongs to a sub-block and 
    the hierarchy of this sub-block is preserved.

当我实现它时我得到这个

WARNING:PhysDesignRules:367 - The signal <BTN_3_IBUF> is incomplete. The signal
    does not drive any load pins in the design.
WARNING:Par:288 - The signal BTN_3_IBUF has no load.  
    PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. 
    This design will cause Bitgen to issue DRC warnings.

当我生成程序文件时，我收到此错误

WARNING:PhysDesignRules:367 - The signal <BTN_3_IBUF> is incomplete. 
    The signal does not drive any load pins in the design.

什么可能导致这个错误.. 代码可以在这里找到 [http://pastebin.com/eK05tyEb][1]

[1]: http://pastebin.com/eK05tyEb http://pastebin.com/eK05tyEb- 链接到代码

用户约束文件/.ucf

NET "Switch_0" LOC = "G18";
    NET "Switch_1" LOC = "H18";
    NET "Switch_2" LOC = "K18";
    NET "Switch_3" LOC = "K17";
    NET "Switch_4" LOC = "L14";
    NET "Switch_5" LOC = "L13";
    NET "Switch_6" LOC = "N17";
    NET "Switch_7" LOC = "R17";
    NET "LED_0" LOC = "J14";
    NET "LED_1" LOC = "J15";
    NET "LED_2" LOC = "K15";
    NET "LED_3" LOC = "K14";
    NET "LED_4" LOC = "E17";
    NET "LED_5" LOC = "P15";
    NET "LED_6" LOC = "F4";
    NET "LED_7" LOC = "R4";
    NET "BTN_3" LOC = "H13";

您发布的代码可能无法讲述整个​​故事。通常有一个接口（用户限制，感谢 Bob）文件定义引脚边缘输入和输出到您定义的 FPGA 内部电路的端口。我没有看到这一点。

其次，我还在您的代码中看到，您有 2 个不同的电路驱动每个输出 LED。

您有一个 if 语句检查 BTN_3 是否为 1，这会将所有 LED 驱动为 0，然后是一组 If 语句检查每个“Switch_X”的输入状态，该语句分别将每个 LED 驱动为 0 或 1。这实际上是非法的。您只能用一个电路来驱动任何输出端口。

你应该做的就是按如下方式编写该电路：

architecture Behavioral of Switch_led is
begin
  Process(Switch_0, Switch_1, Switch_2, Switch_3, Switch_4, Switch_5, Switch_6 , Switch_7, BTN_3)
  begin

    if BTN_3 = '1' then 
      Led_0 <= '0';
      Led_1 <= '0';
      Led_2 <= '0';
      Led_3 <= '0';
      Led_4 <= '0';
      Led_5 <= '0';
      Led_6 <= '0';
      Led_7 <= '0';
    else

      if Switch_0 = '1' then
        Led_0 <= '1';
      else
        Led_0 <= '0';
      end if;

      if Switch_1 = '1' then
        Led_1 <= '1';
      else
        Led_1 <= '0';
      end if;

      if Switch_2 = '1' then
        Led_2 <= '1';
      else
        Led_2 <= '0';
      end if;

      if Switch_3 = '1' then
        Led_3 <= '1';
      else
        Led_3 <= '0';
      end if;

      if Switch_4 = '1' then
        Led_4 <= '1';
      else
        Led_4 <= '0';
      end if;

      if Switch_4 = '1' then
        Led_4 <= '1';
      else
        Led_4 <= '0';
      end if;

      if Switch_5 = '1' then
        Led_5 <= '1';
      else
        Led_5 <= '0';
      end if;

      if Switch_6 = '1' then
        Led_6 <= '1';
      else
        Led_6 <= '0';
      end if;

      if Switch_7 = '1' then
        Led_7 <= '1';
      else
        Led_7 <= '0';
      end if;

    end if;

  end process;
end Behavioral;

我本质上所做的是将所有单独的 Switch_X 检查纳入 btn_3 检查的 else 子句中。这迫使我之前说过，在任何时间点只有一个逻辑电路可以驱动任何 LED。