两个Channel，每个Channel有8个Bank。
对于command和address，采用SDR传输减少总引脚数量。所有的command和address在CLK上升沿锁存。每两个时钟周期传输一个command
对于数据线，采用DDR传输。每个CLK周期有两次数据访问
差分时钟输入（CK_t,CK_c）
双向差分DQS信号
可编程的RL,WL（读延时，写延时）
DMI
Burst Length: 16,32,On-the-fly(16 or 32 sequential)
自动刷新和自刷新
自动温度补偿自刷新
ZQ校准
| Symbol | Type | Description | Remark |
|---|---|---|---|
| CK_t_A, CK_c_A CK_t_B, CK_c_B |
Input | Clock: CK_t and CK_c are differential clock inputs. All address, command and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. AC timings for CA parameters are referenced to CK. Each channel (A & B) has its own clock pair. | 差分时钟信号。每个通道都有自己的差分时钟。地址、命令和控制信号在CK_t的上升沿，CK_c的下降沿被采样 |
| CKE_A CKE_B |
Input | Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock circuits, input buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions. CKE is part of the command code. Each channel (A & B) has its own CKE signal. | 时钟使能，高电平使能。 |
| CS_A CS_B |
Input | Chip Select: CS is part of the command code. Each channel (A & B) has its own CS signal. | |
| CA[5:0]_A, CA[5 0]_B |
Input | Command/Address Inputs: Provide the Command and Address inputs according to the Command Truth Table. Each channel (A&B) has its own CA signals. | CA: Command/Address输入信号。包含命令，地址和Bank的信息。LPDDR4 采用的是CBT（command bus training）的CA training 的过程，在这种方式中，会进行VrefCa，CLK 对CS，CLK 对 CA 的时序调整 |
| ODT_CA_A ODT_CA_B |
Input | CA ODT Control: The ODT_CA pin is used in conjunction with the Mode Register to turn on/off the On-Die-Termination for CA pins. | 终端阻抗的模式控制：一种是使用芯片内部的终端电阻；另一种是外部终端电阻。这个内部电阻随着温度会有细微变化，为了保证信号有准确的终端匹配，需要后面介绍的ZQ。 |
| DQ[15:0]_A, DQ[15:0]_B |
I/O | Data Input/Output : Bi-direction data bus. | 双向数据线 |
| DQS[1:0]_t_A, DQS[1:0]_c_A, DQS[1:0]_t_B, DQS[1:0]_c_B |
I/O | Read Strobe: DQS_t and DQS_c are bi-directional differential output clock signals used to strobe data during a READ or WRITE. The Data Strobe is generated by the DRAM for a READ and is edge-aligned with Data. The Data Strobe is generated by the Memory Controller for a WRITE and is center aligned with Data. Each byte of data has a DataStrobe signal pair. Each channel (A & B) has its own DQS strobes. |
双向数据控制引脚。读和写有各自的DQS信号。当从内存中读取信号时，内存发出DQS，处理器根据这个DQS信号来判断何时接收数据；向内存中写数据时，处理器发出DQS，内存根据DQS来触发数据的接收。读写有各自的DQS就不需要等待DQS反向。 |
| DMI[1:0]_A, DMI[1:0]_B |
I/O | Data Mask Inversion: DMI is a bi-directional signal which is driven HIGH when the data on the data bus is inverted, or driven LOW when the data is in its normal state. Data Inversion can be disabled via a mode register setting. Each byte of data has a DMI signal. Each channel (A & B) has its own DMI signals. |
在读写操作的时候，LPDDR4支持数据翻转(DBIdc)的功能。这个功能的实现是通过读写的时候控制MR3寄存器的对应位来实现的。这个功能可能会在一些软件的特殊应用场景中使用 |
| ZQ | Reference | Calibration Referce: Used to calibrate the output drive strength and the termination resistance. There is one ZQ pin per die. The ZQ pin shall be connected to VDDQ through a 240-Ω ± 1% resistor. | 接低误差的240欧姆电阻。通过片上的ODCE自动校准输出驱动能力和终端匹配电阻。 |
| VDD1, VDD2, VDDQ | Supply | Power Supplies: Isolated on the die for improved noise immunity. | |
| VSS | GND | Ground Reference: Power supply ground reference. | |
| RESET_n | Input | RESET: When asserted LOW, the RESET pin resets both channels of the die. |
LPDDR4每个channel支持8个Bank==>Bank的地址固定是3位。
LPDDR4一般是单Channel大小为2Gb~16Gb。对于汽车中控，一般需要3GB或4GB，因为需要运行Android系统。
对于汽车仪表，TBox+C-V2X，最大2GB就够用。一般1GB~2GB。 单C-V2X或者单环视应用，512MB足够。
LPDDR4的I/O采用LVSTL（低电压摆幅终端逻辑），相对于LPDDR3接口功耗降低50%。
| LPDDR4 | LPDDR3 | |
| 工作电压 | 1.1V，1.8V | 1.2V，1.8V |
| I/O总线时钟 | 1600Mhz, 2133Mhz | 800Mhz |
| 数据传输速率 | 3200MT/s, 4166MT/s | 1600MT/s |
| CA总线 | 6-bit, SDR | 10-bit,DDR |
| 数据总线翻转 | 支持 | 不支持 |
| Die | 支持多Die封装，1、2或4个Die
支持单Die多Channel(1,2,4 ch,16bit/channel) 封装更小。 |
单Die,单Channel |
| ECC | Supported | Not Supported |
推荐的连接方式：红色虚线表示LPDDR4内部的连接
不推荐的连接方式：对于双通道DDR controller来说，内存厂商是不推荐外部挂两个single-die的LPDDR4。走线的分叉影响高速信号的信号质量。
另外，为了layout方便，SoC的DDR controller还支持LPDDR4数据信号的Byte Swap/Bit Swap. 比如i.MX8QXP允许BYTE内交换。
Reference：
1. H9HCNNNBPUMLHR datasheet
2. MX8X_内存应用手册
