1.Report Clock Networks
report_clock_networks -name {network_1}
2.分析设计中逻辑级数的分布
report_design_analysis -logic_level_distribution -logic_level_dist_paths 5000 -name design_analysis_prePlace
3.筛选"clk"时钟域逻辑级数在[a,b]之间的c条路径
report_timing -name longPaths -of_objects [get_timing_paths -setup -to [get_clocks clk] -max_paths c -filter {LOGIC_LEVELS>=a && LOGIC_LEVELS<=b}]
4.扇出分析 扇出大于a的b条路经
report_high_fanout_nets -fanout_greater_than a -max_nets b
5 freq & level
125M以下:13级
125-250: 6级
250-350: 5级
350-400: 4级
400以上: 3级
6 门控时钟插入设置
控制芯片中,对不同位宽的寄存器是否自动插入CG
set_clock_gating_style -minimum_bitwidth 4
7 TCL命令查找信号
select_objects [get_cells
{design_1_i/pingpang_write_buff_0/inst/FSM_sequential_ram_wr_state[0]_i_2}]