quartus 中出现的问题总结

quartus 中出现的问题总结

下面展示报错。

// A code block
#Start time: 16:27:28 on Mar 25,2020
# ** Error: (vsim-3170) Could not find 'fulladder1_vlg_tst'.
#         Searched libraries:
#             F:/Quartus_prime0225/modelsim_ase/altera/verilog/altera
#             F:/Quartus_prime0225/modelsim_ase/altera/verilog/cycloneive
#             F:/Quartus_prime0225/adder/simulation/modelsim/gate_work
#             F:/Quartus_prime0225/adder/simulation/modelsim/gate_work
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./adder_run_msim_gate_verilog.do PAUSED at line 12

报错原因：
module名称与testbench以及最初编译的.v/.bdf文件名不同。更改即可。