回到顶层Makefile,有以下内容:
$(vmlinux-dirs): prepare scripts
$(Q)$(MAKE) $(build)=$@
vmlinux-dirs
包含要构建的子目录列表(init, usr, kernel, ETC。)。$(Q)$(MAKE) $(build)=<subdirectory>
将为每个子目录运行。
上面的规则编译内核映像和模块的目标文件。在顶层 Makefile 的更下方,还有一些额外的特定于模块的内容:
ifdef CONFIG_MODULES
...
modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux) modules.builtin
# Do additional module-specific stuff using
# scripts/Makefile.modpost among other things
# (my comment).
...
...
endif # CONFIG_MODULES
调查scripts/Makefile.build
(使用的 Makefile$(build)
)现在,它首先初始化obj-*
列表和各种其他列表:
# Init all relevant variables used in kbuild files so
# 1) they have correct type
# 2) they do not inherit any value from the environment
obj-y :=
obj-m :=
lib-y :=
lib-m :=
再往下一点,它加载到 Kbuild 文件中,其中obj-y
, obj-m
等,设置:
include $(kbuild-file)
再往下是默认规则,其中有$(obj-y)
and $(obj-m)
列出先决条件:
__build: $(if $(KBUILD_BUILTIN),$(builtin-target) $(lib-target) $(extra-y)) \
$(if $(KBUILD_MODULES),$(obj-m) $(modorder-target)) \
$(subdir-ym) $(always)
@:
The $(obj-y)
前提条件来自于$(builtin-target)
,其定义如下:
builtin-target := $(obj)/built-in.o
...
$(builtin-target): $(obj-y) FORCE
$(call if_changed,link_o_target)
实际的构建似乎是按照以下规则进行的:
# Built-in and composite module parts
$(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
$(call cmd,force_checksrc)
$(call if_changed_rule,cc_o_c)
if_changed_rule
来自Kbuild.include
。该规则最终运行以下命令Makefile.build
:
define rule_cc_o_c
$(call echo-cmd,checksrc) $(cmd_checksrc) \
$(call echo-cmd,cc_o_c) $(cmd_cc_o_c); \
...
endef
$(cmd_cc_o_c)
似乎是实际的编译命令。通常的定义(有两种可能Makefile.build
,AFAICS)似乎如下:
cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
除非明确设置使用例如make CC=clang
, CC
默认为gcc
,如顶级 Makefile 中所示:
ifneq ($(CC),)
ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
COMPILER := clang
else
COMPILER := gcc
endif
export COMPILER
endif