【VHDL】分频器设计要求:25分频,占空比为50%
程序`
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; entity DIV_25 IS PORT(CLK:IN STD_LOGIC; S1,S2:BUFFER STD_LOGIC; CNT:BUFFER INTEGER; Q:OUT STD_LOGIC); END ENTITY; ARCHITECTURE ONE OF DIV_25 IS BEGIN