This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2s, but using asynchronous reset.
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
state <= next_state;
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset == 1)
next_state <= OFF;
else case (next_state)
OFF: if(j == 1)
next_state <= ON;
else
next_state <= OFF;
ON : if(k == 1)
next_state <= OFF;
else
next_state <= ON;
default:
next_state <= OFF;
endcase
end
// Output logic
// assign out = (state == ...);
assign out = state == ON ? 1'b1 : 1'b0;
endmodule