来自不同进程的VHDL驱动信号

我对以下 VHDL 代码有一个小问题：

process (zbroji)
begin
    if rising_edge(zbroji) then
        oduzima <= '0';
        ucitanPrvi <= '1';
        broj1 <= ulaz_broj;
    end if;
end process;

process (oduzmi)
begin
    if rising_edge(oduzmi) then
        oduzima <= '1';
        ucitanPrvi <= '1';
        broj1 <= ulaz_broj;
    end if;

end process;

问题是信号 ucitanPrvi 总是具有值 X。如果我不尝试在两个进程中设置它的值，那么我就没有任何问题......所以我知道我不能从多个进程驱动一个信号，但我不知道如何以不同的方式写这个...... 有谁知道我如何解决这个问题？

Thanks !

编辑：谢谢大家的回复:)现在我明白为什么我不能从多个进程驱动一个信号（至少以我希望它工作的方式）。

如果您想综合真实 FPGA 或 ASIC 的设计，则必须从真实硬件（线路、触发器、门等）角度考虑 VHDL。此外，如果您想在硬件中执行真正的上升沿检测，您将需要一个驱动触发器的系统时钟。鉴于您的原始代码示例， zbroji 或 oduzmi 似乎不是系统时钟，而只是 std_logic 信号。我编写了这个代码示例，假设您的示例具有基本功能，希望您可以采用我的代码和注释并完成您需要的功能。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity example is
  port (Reset      : in  std_logic;
        SysClk     : in  std_logic;
        zbroji     : in  std_logic;
        oduzmi     : in  std_logic;
        ulaz_broj  : in  std_logic;
        oduzima    : out std_logic;
        ucitanPrvi : out std_logic;
        broj1      : out std_logic
        );

end example;

architecture Behavioral of example is

  -- Delayed version of input signals (1 clock cycle delay)
  signal zbroji_d : std_logic;
  signal oduzmi_d : std_logic;

  signal zbrojiRE : std_logic;
  signal oduzmiRE : std_logic;

begin

  -- Generate 1 clock cycle delayed version of
  -- signals we want to detect the rising edge
  -- Assumes active high reset
  -- Note: You should only use the rising_edge macro
  -- on an actual global or regional clock signal. FPGA's and
  -- ASICs place timing constraints on defined clock signals
  -- that make it possible to use rising_edge, otherwise, we have
  -- to generate our own rising edge signals by comparing delayed
  -- versions of a signal with the current signal.
  -- Also, with any respectable synthesizer / simulator using
  -- rising_edge is almos exactly the same as (clk'event and clk='1')
  -- except rising_edge only returns a '1' when the clock makes a
  -- valid '0' to '1' transition. (see link below)
  EdgeDetectProc : process (Reset, SysClk)
  begin
    if Reset = '1' then
      zbroji_d <= '0';
      oduzmi_d <= '0';
    elsif rising_edge(SysClk) then
      zbroji_d <= zbroji;
      oduzmi_d <= oduzmi;
    end if;
  end process EdgeDetectProc;

  -- Assert risinge edge signals for one clock cycle 
  zbrojiRE <= '1' when zbroji = '1' and zbroji_d = '0' else '0';
  oduzmiRE <= '1' when oduzmi = '1' and oduzmi_d = '0' else '0';

  -- Assumes that you want a single cycle pulse on ucitanPrvi on the
  -- rising edege of zbroji or oduzmi;
  ucitanPrvi <= zbrojiRE or oduzmiRE;

  -- Based on your example, I can't tell what you want to do with the
  -- broj1 signal, but this logic will drive broj1 with ulaz_broj on
  -- either the zbroji or oduzmi rising edge, otherwise '0'.
  broj1 <= ulaz_broj when zbrojiRE = '1' else
           ulaz_broj when oduzmiRE = '1' else
           '0';

  -- Finally, it looks like you want to clear oduzima on the rising
  -- edge of zbroji and assert oduzima on the rising edge of
  -- oduzmi
  LatchProc : process (Reset, SysClk)
  begin
    if Reset = '1' then
      oduzima <= '0';
    elsif rising_edge(SysClk) then
      if zbrojiRE = '1' then
        oduzima <= '0';
      elsif oduzmiRE = '1' then
        oduzima <= '1';
      end if;
    end if;
  end process LatchProc;

end Behavioral;

前面的代码假设您有一个系统时钟。在像 ModelSim（免费学生版）这样的模拟器中，您可以使用不可综合的测试平台代码生成 100 MHz 时钟，如下所示...

ClockProc : process
begin 
   SysClk <= '0';
   wait for 5 ns;
   SysClk <= '1';
   wait for 5 ns;
end process ClockProc;

在实际的 FPGA/ASIC 实现中，您可能需要使用芯片中运行的外部振荡器，将信号驱动到 DCM（数字时钟管理器），它将向所有 VHDL 逻辑输出非常干净的时钟信号，这样您就可以获得无故障的设计。

最后，这是关于rising_edge和rising_edge之间差异的一个很好的解释 (clk'事件和clk='1')

http://vhdlguru.blogspot.com/2010/04/difference- Between-risingedgeclk-and.html

希望有帮助。