See also: State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)
module top_module(
input clk,
input in,
input reset,
output out); //
parameter A =2'b00,
B = 2'b01,
C = 2'b11,
D = 2'b10;
reg [1:0] state;
reg [1:0] next_state;
// State transition logic
always@ (posedge clk)
if(reset)
next_state <= A;
else case (next_state)
A : if(in == 1)
next_state <= B;
else
next_state <= A;
B : if(in == 0)
next_state <= C;
else
next_state <= B;
C : if(in == 1)
next_state <= D;
else
next_state <= A;
D : if(in == 1)
next_state <= B;
else
next_state <= C;
default:next_state <= A;
endcase
// State flip-flops with synchronous reset
always@(*) begin
state <= next_state;
end
// Output logic
assign out = state == D ? 1'b1 : 1'b0;
endmodule