module decode_38 (
input wire[2:0] a,
output reg[7:0] y
);
integer i;
always @(*) begin //******
for (i=0;i<8;i=i+1) begin
if (a==i)
y[i]<=1;
else y[i]<=0;
end
end
endmodule
module decode_38_tb;
reg A,B,C;
wire [7:0] y;
wire [2:0] a;
assign a={A,B,C};
decode_38 D(.a(a),
.y(y)
);
initial begin
A=0;B=0;C=0;#100;
A=0;B=0;C=1;#100;
A=0;B=1;C=0;#100;
A=0;B=1;C=1;#100;
A=1;B=0;C=0;#100;
A=1;B=0;C=1;#100;
A=1;B=1;C=0;#100;
A=1;B=1;C=1;#100;
end
endmodule
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